Online MIPS Assembler for (System)Verilog

This is a modified version of the online MIPS assembler found at https://github.com/bilkentCraps/mips. The main differences are as follows:

1. This assembler is able to parse hexadecimal and binary numbers
2. The adr field of J-Type instructions are interpreted as memory addresses instead of line numbers
3. This assembler supports using the shamt field for R-type instructions
4. If the default instruction definitions are used, the immediate used in the beq instruction is interpreted as an offset from the next line (that is, beq $zero, $zero, -1 results in an infinite loop)

The left textbox contains the instruction definitions, the middle textbox contains the assembly code, and the right textbox contains the code to paste inside the imem module

You can refer to the README of the original assembler for more info (keep in mind the differences listed above): https://github.com/bilkentCraps/mips/blob/gh-pages/README.md

j adr = 000010 adr addi rt rs imm = 001000 rs rt imm beq rs rt imm = 000100 rs rt imm sw rt imm rs = 101011 rs rt imm lw rt imm rs = 100011 rs rt imm or rd rs rt = 000000 rs rt rd 00000 100101 and rd rs rt = 000000 rs rt rd 00000 100100 add rd rs rt = 000000 rs rt rd 00000 100000 slt rd rs rt = 000000 rs rt rd 00000 101010 sub rd rs rt = 000000 rs rt rd 00000 100010 addi $t0, $zero, 5 addi $t1, $zero, 3 beq $t0, $t1, 2 add $t2, $t1, $t0 sub $t0, $t0, $t1 addi $t1, $t1, -1 beq $t1, $t0, 2 sw $t2, 0x50($zero) or $t0, $t1, $t0 slt $t1, $t1, $t0 beq $t1, $zero, 2 lw $t3, 0x50($zero) and $t0, $t1, $t0 beq $t0, $t0, -1 # So it loops here